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» System Level Hardware-Software Design Exploration with XCS
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ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 2 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
TEI
2010
ACM
199views Hardware» more  TEI 2010»
14 years 3 months ago
Revealing the invisible: visualizing the location and event flow of distributed physical devices
Distributed physical user interfaces comprise networked sensors, actuators and other devices attached to a variety of computers in different locations. Developing such systems is ...
Nicolai Marquardt, Tom Gross, M. Sheelagh T. Carpe...
ICRA
2005
IEEE
137views Robotics» more  ICRA 2005»
14 years 2 months ago
Learning Opportunity Costs in Multi-Robot Market Based Planners
— Direct human control of multi-robot systems is limited by the cognitive ability of humans to coordinate numerous interacting components. In remote environments, such as those e...
Jeff G. Schneider, David Apfelbaum, Drew Bagnell, ...
VIS
2004
IEEE
115views Visualization» more  VIS 2004»
14 years 10 months ago
Visualization in Grid Computing Environments
Grid computing provides a challenge for visualization system designers. In this research, we evolve the dataflow concept to allow parts of the visualization process to be executed...
Ken Brodlie, David A. Duce, Julian R. Gallop, Musb...
DAC
2006
ACM
14 years 10 months ago
Programming models and HW-SW interfaces abstraction for multi-processor SoC
ing models and HW-SW Interfaces Abstraction for Multi-Processor SoC Ahmed A. Jerraya TIMA Laboratory 46 Ave Felix Viallet 38031 Grenoble CEDEX, France +33476574759 Ahmed.Jerraya@im...
Ahmed Amine Jerraya, Aimen Bouchhima, Fréd&...