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» System issues in boundary-scan board test
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ITC
2000
IEEE
76views Hardware» more  ITC 2000»
13 years 12 months ago
System issues in boundary-scan board test
Boards have evolved into complex systems and even collections of interacting systems. Test engineers struggle to find out how these systems are initialized and booted because of p...
Kenneth P. Parker
DATE
1999
IEEE
85views Hardware» more  DATE 1999»
13 years 11 months ago
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
Jongchul Shin, Hyunjin Kim, Sungho Kang
ITC
2003
IEEE
110views Hardware» more  ITC 2003»
14 years 22 days ago
An extension to JTAG for at-speed debug on a system
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to che...
Leon van de Logt, Frank van der Heyden, Tom Waayer...
AIMSA
2008
Springer
14 years 1 months ago
Tailoring the Interpretation of Spatial Utterances for Playing a Board Game
In order to build an intelligent system that allows human beings to cooperate with a computing machine to perform a given task it is important to account for the individual charact...
Andrea Corradini
MSE
2005
IEEE
133views Hardware» more  MSE 2005»
14 years 1 months ago
Embedded System Design with FPGAs Using HDLs (Lessons Learned and Pitfalls to Be Avoided)
This paper describes the authors experience with teaching VHDL (and more recently, Verilog) to undergraduate and graduate students at WPI and to engineers through various short co...
R. James Duckworth