60 search results - page 5 / 12 » System level clock tree synthesis for power optimization |
DAC
2008
ACM
13 years 8 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
DAC
1998
ACM
13 years 11 months ago
1998
ACM
We present a technique for synthesizing power- as well as area-optimized circuits from hierarchical data flow graphs under throughput constraints. We allow for the use of complex...
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
ISSS
1997
IEEE
13 years 11 months ago
1997
IEEE
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
DATE
1997
IEEE
13 years 11 months ago
1997
IEEE
A design methodology for the synthesis of digital circuits used in high throughput digital modems is presented. The methodology spans digital modem design from the link level to t...