169 search results - page 2 / 34 » System level memory optimization for hardware-software co-de... |
DATE
2005
IEEE
14 years 29 days ago
2005
IEEE
With the advent of multi-processor systems on a chip, the interest for message passing libraries has revived. Message passing helps in mastering the design complexity of parallel ...
VLSID
2008
IEEE
14 years 7 months ago
2008
IEEE
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
ISSS
1996
IEEE
13 years 11 months ago
1996
IEEE
The paper presents two heuristics for hardware/software partitioning of system level specifications. The main objective is to achieve performance optimization with a limited hardw...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...