Sciweavers

897 search results - page 163 / 180
» System-Level Design for FPGAs
Sort
View
ISLPED
2007
ACM
99views Hardware» more  ISLPED 2007»
13 years 11 months ago
Thermal-aware task scheduling at the system software level
Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an ad...
Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, H...
DAC
2005
ACM
14 years 10 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 6 months ago
Platform-based resource binding using a distributed register-file microarchitecture
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
Jason Cong, Yiping Fan, Wei Jiang
FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
14 years 4 months ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon
FCCM
2008
IEEE
212views VLSI» more  FCCM 2008»
14 years 4 months ago
Map-reduce as a Programming Model for Custom Computing Machines
The map-reduce model requires users to express their problem in terms of a map function that processes single records in a stream, and a reduce function that merges all mapped out...
Jackson H. C. Yeung, C. C. Tsang, Kuen Hung Tsoi, ...