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    ISLPED
    2005
    ACM
    150views Hardware» more  ISLPED 2005»
    Fast configurable-cache tuning with a unified second-level cache
    14 years 3 months ago
    Fast configurable-cache tuning with a unified second-level cache
    Download  www.cs.ucr.edu
    Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
    Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
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    GLVLSI
    2010
    IEEE
    187views VLSI» more  GLVLSI 2010»
    Write activity reduction on flash main memory via smart victim cache
    14 years 3 months ago
    Write activity reduction on flash main memory via smart victim cache
    Download  www.utdallas.edu
    Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
    Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
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    IJHPCA
    2008
    75views more  IJHPCA 2008»
    Towards Ultra-High Resolution Models of Climate and Weather
    13 years 10 months ago
    Towards Ultra-High Resolution Models of Climate and Weather
    Download  www.nersc.gov
    We present a speculative extrapolation of the performance aspects of an atmospheric general circulation model to ultra-high resolution and describe alternative technological paths...
    Michael F. Wehner, Leonid Oliker, John Shalf
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    IJCSA
    2008
    237views more  IJCSA 2008»
    Development of A SOLAP Patrimony Management Application System: Fez Medina as a Case Study
    13 years 10 months ago
    Development of A SOLAP Patrimony Management Application System: Fez Medina as a Case Study
    Download  www.tmrfindia.org
    It is well known that transactional and analytical systems each require different database architecture. In general, the database structure of transactional systems is optimized f...
    I. Salam, M. El Mohajir, A. Taleb, B. El Mohajir
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    CODES
    2006
    IEEE
    183views Software Engineering» more  CODES 2006»
    Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
    14 years 4 months ago
    Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
    Download  www.cecs.uci.edu
    The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
    Ilya Issenin, Nikil Dutt
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