Sciweavers

816 search results - page 21 / 164
» System-Level Power Performance Analysis for Embedded Systems...
Sort
View
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 1 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
ASPDAC
2007
ACM
133views Hardware» more  ASPDAC 2007»
13 years 11 months ago
RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip
Abstract-- Multiprocessor designs have become popular in embedded domains for achieving the power and performance requirements. In this paper, we present principles and techniques ...
Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada
CODES
2011
IEEE
12 years 7 months ago
Design and architectures for dependable embedded systems
The paper presents an overview of a major research project on dependable embedded systems that has started in Fall 2010 and is running for a projected duration of six years. Aim i...
Jörg Henkel, Lars Bauer, Joachim Becker, Oliv...
CODES
2004
IEEE
13 years 11 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
WOSP
2004
ACM
14 years 1 months ago
Early-stage performance modeling and its application for integrated embedded control software design
Most of current embedded control software (ECSW) development techniques deal only with performance specifications during the early software design phase and delay the modeling and...
Shige Wang, Kang G. Shin