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ICC
2007
IEEE
135views Communications» more  ICC 2007»
14 years 2 months ago
New Results on Single-Step Power Control System in Finite State Markov Channel: Power Control Error Modelling and Queueing Varia
— The analysis regarding the impact of the single-step power control (SSPC) scheme on the system performance such as bit error rate, packet error rate and queueing variation is h...
Shi-Yong Lee, Min-Kuan Chang
DSD
2011
IEEE
194views Hardware» more  DSD 2011»
12 years 7 months ago
Reliability-Aware Design Optimization for Multiprocessor Embedded Systems
—This paper presents an approach for the reliability-aware design optimization of real-time systems on multi-processor platforms. The optimization is based on an extension of wel...
Jia Huang, Jan Olaf Blech, Andreas Raabe, Christia...
DAC
2008
ACM
14 years 8 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
ECRTS
2005
IEEE
14 years 1 months ago
Speed Modulation in Energy-Aware Real-Time Systems
This paper presents a general framework for analyzing and designing embedded systems with energy and timing requirements. A set of realistic assumptions is considered in the model...
Enrico Bini, Giorgio C. Buttazzo, Giuseppe Lipari
VLSID
2004
IEEE
170views VLSI» more  VLSID 2004»
14 years 8 months ago
On-chip networks: A scalable, communication-centric embedded system design paradigm
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
Jörg Henkel, Srimat T. Chakradhar, Wayne Wolf