93 search results - page 10 / 19 » System-level memory modeling for bus-based memory architectu... |
SPAA
1995
ACM
14 years 2 days ago
1995
ACM
For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent yea...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
EUROCAST
2003
Springer
14 years 1 months ago
2003
Springer
This paper explores the computational capacity of a novel local computational model that expands the conventional analogical and logical dynamic neural models, based on the charge ...