93 search results - page 8 / 19 » System-level memory modeling for bus-based memory architectu... |
126
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VLSID
2008
IEEE
16 years 4 months ago
2008
IEEE
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
148
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IPPS
2002
IEEE
15 years 9 months ago
2002
IEEE
The increasing gap between processor and memory performance has led to new architectural models for memory-intensive applications. In this paper, we use a set of memory-intensive ...
131
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ICS
1999
Tsinghua U.
15 years 8 months ago
1999
Tsinghua U.
Programming languages that provide multidimensional arrays and a flat linear model of memory must implement a mapping between these two domains to order array elements in memory....
142
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DATE
2002
IEEE
15 years 9 months ago
2002
IEEE
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
168
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ASPLOS
2006
ACM
15 years 7 months ago
2006
ACM
Architects use cycle-by-cycle simulation to evaluate design choices and understand tradeoffs and interactions among design parameters. Efficiently exploring exponential-size desig...