392 search results - page 7 / 79 » System-level power estimation and optimization |
TVLSI
2010
13 years 4 months ago
2010
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
ISLPED
2007
ACM
13 years 11 months ago
2007
ACM
RTL power macromodeling is a mature research topic with a variety of equation and table-based approaches. Despite its maturity, macromodeling is not yet widely accepted as an indu...
PATMOS
2004
Springer
14 years 3 months ago
2004
Springer
We present SoftExplorer, a tool to estimate and analyze the power and energy consumption of an algorithm from the C program. The consumption of every loop is analyzed, and the inï¬...
ICCAD
1997
IEEE
14 years 1 months ago
1997
IEEE
Maximum instantaneous power in VLSI circuits has a great impact on circuit's reliability and the design of power and ground lines. To synthesizehighlyreliablesystems,accurate...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
- Each year tens of billions of Dollars are wasted by the microelectronics industry because of missed deadlines and delayed design projects. These delays are partially due to desig...