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» System-level power optimization: techniques and tools
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ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
14 years 1 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 8 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
DAC
2010
ACM
13 years 12 months ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...
HPDC
2008
IEEE
14 years 2 months ago
Ontological framework for a free-form query based grid search engine
If the model of free-form queries, which has proved successful for HTML based search on the Web, is made available for Grid services, it will serve as a powerful tool for scientis...
Chaitali Gupta, Rajdeep Bhowmik, Madhusudhan Govin...
BMCBI
2004
150views more  BMCBI 2004»
13 years 7 months ago
SS-Wrapper: a package of wrapper applications for similarity searches on Linux clusters
Background: Large-scale sequence comparison is a powerful tool for biological inference in modern molecular biology. Comparing new sequences to those in annotated databases is a u...
Chunlin Wang, Elliot J. Lefkowitz