54 search results - page 4 / 11 » Teaching Hardware Description and Verification |
DAC
2001
ACM
14 years 8 months ago
2001
ACM
New application-focused system-on-chip platforms motivate new application-specific processors. Configurable and extensible processor architectures offer the efficiency of tuned lo...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
ATVA
2009
Springer
13 years 11 months ago
2009
Springer
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mi...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
—In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining faultinjection in high level design (HLD) descriptions with a forma...