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ICCAD
2008
IEEE
153views Hardware» more  ICCAD 2008»
16 years 1 months ago
Boolean factoring and decomposition of logic networks
This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut based view of a logic network, 2) exploiting th...
Alan Mishchenko, Robert K. Brayton, Satrajit Chatt...
3DIC
2009
IEEE
146views Hardware» more  3DIC 2009»
15 years 11 months ago
A routerless system level interconnection network for 3D integrated systems
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
Kelli Ireland, Donald M. Chiarulli, Steven P. Levi...
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
15 years 11 months ago
aEqualized: A novel routing algorithm for the Spidergon Network On Chip
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...
Nicola Concer, Salvatore Iamundo, Luciano Bononi
ICECCS
2009
IEEE
129views Hardware» more  ICECCS 2009»
15 years 11 months ago
CONNECT Challenges: Towards Emergent Connectors for Eternal Networked Systems
—The CONNECT European project that started in February 2009 aims at dropping the interoperability barrier faced by today’s distributed systems. It does so by adopting a revolut...
Valérie Issarny, Bernhard Steffen, Bengt Jo...
DATE
2008
IEEE
81views Hardware» more  DATE 2008»
15 years 10 months ago
Practical Implementation of a Network Analyzer for Analog BIST Applications
This paper presents a practical implementation of a network analyzer for analog BIST applications. The network analyzer consists of a sinewave generator and a sinewave evaluator b...
Manuel J. Barragan Asian, Diego Vázquez, Ad...