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MICRO
1993
IEEE
128views Hardware» more  MICRO 1993»
13 years 10 months ago
Techniques for extracting instruction level parallelism on MIMD architectures
Extensive research has been done on extracting parallelism from single instruction stream processors. This paper presents some results of our investigation into ways to modify MIM...
Gary S. Tyson, Matthew K. Farrens
MICRO
1991
IEEE
115views Hardware» more  MICRO 1991»
13 years 10 months ago
Executing Loops on a Fine-Grained MIMD Architecture
- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processor...
Sunah Lee, Rajiv Gupta
ISCAPDCS
2007
13 years 8 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
14 years 28 days ago
Mapping the physical layer of radio standards to multiprocessor architectures
We are concerned with the software implementation of baseband processing for the physical layer of radio standards (“Software Defined Radio - SDR”). Given the constraints for ...
Cyprian Grassmann, Mathias Richter, Mirko Sauerman...
DATE
2005
IEEE
151views Hardware» more  DATE 2005»
14 years 6 days ago
Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications
Instruction Level Parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and...
Domenico Barretta, William Fornaciari, Mariagiovan...