Sciweavers

11 search results - page 2 / 3
» Technology Mapping for Speed-Independent Circuits: Decomposi...
Sort
View
ICCAD
1997
IEEE
100views Hardware» more  ICCAD 1997»
13 years 12 months ago
Decomposition and technology mapping of speed-independent circuits using Boolean relations
Jordi Cortadella, Michael Kishinevsky, Alex Kondra...
FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
14 years 3 days ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong
DAC
1996
ACM
13 years 11 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl
FPGA
2007
ACM
185views FPGA» more  FPGA 2007»
14 years 1 months ago
Power-aware FPGA logic synthesis using binary decision diagrams
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
Kevin Oo Tinmaung, David Howland, Russell Tessier
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
13 years 11 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat