171 search results - page 4 / 35 » Technology mapping for domino logic |
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
DAC
1998
ACM
14 years 8 months ago
1998
ACM
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
DAC
1994
ACM
13 years 11 months ago
1994
ACM
- This paper presents a placement-driven technology mapping procedure based on fuzzy delay curves. The fuzziness has been introduced to deal with the inherent vagueness in wiring l...
TCAD
2008
13 years 7 months ago
2008
Abstract--This paper proposes an adaptive watermarking technique by modulating some closed cones in an originally optimized logic network (master design) for technology mapping. Th...