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» Technology mapping for k m-macrocell based FPGAs
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ICCAD
2004
IEEE
123views Hardware» more  ICCAD 2004»
14 years 4 months ago
Logical effort based technology mapping
We propose a new approach to library-based technology mapping, based on the method of logical effort. Our algorithm is close to optimal for fanout-free circuits, and is extended t...
Shrirang K. Karandikar, Sachin S. Sapatnekar
FPGA
2008
ACM
308views FPGA» more  FPGA 2008»
13 years 9 months ago
Fpga-based data acquisition system for a positron emission tomography (PET) scanner
: Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates of above 100MHz. This combined with FPGAs l...
Michael Haselman, Robert Miyaoka, Thomas K. Lewell...
FPGA
2006
ACM
131views FPGA» more  FPGA 2006»
13 years 11 months ago
Yield enhancements of design-specific FPGAs
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
FPL
2006
Springer
99views Hardware» more  FPL 2006»
13 years 11 months ago
Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs
As manufacturing technology enters the ultra-deep submicron era, wafer yields are destined to drop due to higher occurrence of physical defects on the die. This paper proposes a y...
Nicola Campregher, Peter Y. K. Cheung, George A. C...
DAC
1996
ACM
14 years 5 days ago
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...
Jason Cong, Yean-Yow Hwang