32 search results - page 4 / 7 » Temporal instruction fetch streaming |
IEEEPACT
2005
IEEE
14 years 1 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...
VIP
2001
13 years 8 months ago
2001
It is often necessary to reduce storage and bandwidth requirements when recording or broadcasting a sequence of actions on a computer screen. These applications most commonly fall...
SASP
2009
IEEE
14 years 2 months ago
2009
IEEE
—Multi-cycle Instruction set extensions (ISE) can be pipelined in order to increase their throughput; however, typical program traces seldom contain consecutive calls to the same...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...