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» Tera-scale computing and interconnect challenges
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2005
ACM
14 years 4 days ago
Viable opto-electronic HPC interconnect fabrics
We address the problem of how to exploit optics for ultrascale High Performance Computing interconnect fabrics. We show that for high port counts these fabrics require multistage ...
Ronald P. Luijten, Cyriel Minkenberg, B. Roe Hemen...
DAC
2002
ACM
14 years 7 months ago
The next chip challenge: effective methods for viable mixed technology SoCs
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
H. Bernhard Pogge
ISCAS
2008
IEEE
110views Hardware» more  ISCAS 2008»
14 years 1 months ago
Non-traditional irregular interconnects for massive scale SoC
— By using self-assembling fabrication techniques at the cellular, molecular, or atomic scale, it is nowadays possible to create functional assemblies in a mainly bottom-up way t...
Christof Teuscher, Anders A. Hansson
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 19 days ago
Contrasting a NoC and a traditional interconnect fabric with layout awareness
Increasing miniaturization is posing multiple challenges to electronic designers. In the context of Multi-Processor System-onChips (MPSoCs), we focus on the problem of implementin...
Federico Angiolini, Paolo Meloni, Salvatore Carta,...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 7 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...