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DATE
2004
IEEE
120views Hardware» more  DATE 2004»
13 years 11 months ago
Pattern Selection for Testing of Deep Sub-Micron Timing Defects
Due to process variations in deep sub-micron (DSM) technologies, the effects of timing defects are difficult to capture. This paper presents a novel coverage metric for estimating...
Mango Chia-Tso Chao, Li-C. Wang, Kwang-Ting Cheng
DAGSTUHL
2001
13 years 9 months ago
Understanding Algorithms by Means of Visualized Path Testing
Visualization of an algorithm offers only a rough picture of operations. Explanations are crucial for deeper understanding, because they help the viewer to associate the visualiza...
Ari Korhonen, Erkki Sutinen, Jorma Tarhio
ITC
1997
IEEE
73views Hardware» more  ITC 1997»
13 years 11 months ago
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
Indradeep Ghosh, Niraj K. Jha, Sujit Dey
GECCO
2005
Springer
113views Optimization» more  GECCO 2005»
14 years 1 months ago
Estimating the detector coverage in a negative selection algorithm
This paper proposes a statistical mechanism to analyze the detector coverage in a negative selection algorithm, namely a quantitative measurement of a detector set’s capability ...
Zhou Ji, Dipankar Dasgupta
ICCAD
1999
IEEE
86views Hardware» more  ICCAD 1999»
13 years 12 months ago
A framework for testing core-based systems-on-a-chip
Available techniques for testing core-based systems-on-a-chip (SOCs) do not provide a systematic means for synthesising low-overhead test architectures and compact test solutions....
Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jh...