203 search results - page 16 / 41 » Test Generation and Fault Localization for Quantum Circuits |
ITC
1993
IEEE
13 years 11 months ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
DATE
1999
IEEE
13 years 11 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
Test sets that detect each target fault n times (n-detection test sets) are typically generated for restricted values of n due to the increase in test set size with n. We perform ...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
ASPDAC
1998
ACM
13 years 11 months ago
1998
ACM
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...