1016 search results - page 21 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ISLPED
2006
ACM
14 years 1 months ago
2006
ACM
—The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or alteri...
ICTAI
2002
IEEE
14 years 17 days ago
2002
IEEE
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
HICSS
1998
IEEE
13 years 12 months ago
1998
IEEE
This paper describes the uses and architecture of a network-centered computing-rich software platform called PowerWeb. PowerWeb was designed and built as a simulation environment ...
IOLTS
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper proposes a new test pattern generator (TPG) which is an enhancement of GLFSR (Galois LFSR). This design is based on certain non–binary error detecting codes, formulat...
ISCAS
1999
IEEE
13 years 12 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...