1016 search results - page 40 / 204 » Test Generation for Designs with On-Chip Clock Generators |
118
click to vote
ICCD
2001
IEEE
16 years 19 days ago
2001
IEEE
CMOS Phase-locked loops (PLL) are ubiquitous in RF and mixed-signal integrated circuits. PLLs are very sensitive to noise fluctuations on the power and ground rails. In this paper...
98
Voted
IFIP
1999
Springer
15 years 8 months ago
1999
Springer
: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
113
Voted
DAC
1997
ACM
15 years 8 months ago
1997
ACM
We examine frequency-domain issues in the design and selection of on-chip test generators for built-in self-test (BIST) of highperformance digital filters. Test-generator/circuit...
126
Voted
WSC
2001
15 years 5 months ago
2001
The requirements, design principles, and statistical testing approaches of uniform random number generators for simulation are briefly surveyed. An objectoriented random number pa...
125
Voted
EDM
2009
15 years 1 months ago
2009
This paper describes a novel method to create a quantitative model of an educational content domain of related practice item-types using learning curves. By using a pairwise test t...