1016 search results - page 70 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
Current design automation methodologies are becoming incapable of achieving design closure especially in the presence of deep submicron effects. This paper addresses the issue of ...
ICCAD
1999
IEEE
14 years 2 days ago
1999
IEEE
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
DSD
2002
IEEE
14 years 22 days ago
2002
IEEE
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...