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» Test Resource Partitioning and Optimization for SOC Designs
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ICCD
2006
IEEE
125views Hardware» more  ICCD 2006»
14 years 5 months ago
Partial Functional Manipulation Based Wirelength Minimization
—In-place flipping of rectangular blocks/cells can potentially reduce the wirelength of a floorplan/placement solution without changing the chip area, In a recent work [Hao 05], ...
Avijit Dutta, David Z. Pan
CODES
2004
IEEE
14 years 10 days ago
Automatic synthesis of system on chip multiprocessor architectures for process networks
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishna...
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
14 years 2 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
14 years 27 days ago
Power minimization using system-level partitioning of applications with quality of service requirements
Design systems to provide various quality of service (QoS) guarantees has received a lot of attentions due to the increasing popularity of real-time multimedia and wireless commun...
Gang Qu, Miodrag Potkonjak
DATE
2008
IEEE
115views Hardware» more  DATE 2008»
14 years 3 months ago
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi