145 search results - page 4 / 29 » Test Resource Partitioning and Optimization for SOC Designs |
VTS
2002
IEEE
14 years 1 months ago
2002
IEEE
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
ICCAD
2003
IEEE
14 years 5 months ago
2003
IEEE
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
ATS
2002
IEEE
14 years 1 months ago
2002
IEEE
Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper, we survey recent advances in test planning that addre...
ET
2002
13 years 8 months ago
2002
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...