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ICCD
2004
IEEE
109views Hardware» more  ICCD 2004»
14 years 4 months ago
Low Power Test Data Compression Based on LFSR Reseeding
Many test data compression schemes are based on LFSR reseeding. A drawback of these schemes is that the unspecified bits are filled with random values resulting in a large number ...
Jinkyu Lee, Nur A. Touba
ICCAD
2007
IEEE
109views Hardware» more  ICCAD 2007»
13 years 11 months ago
CacheCompress: a novel approach for test data compression with cache for IP embedded cores
Abstract-- In this paper, we propose a novel test data compression technique named CacheCompress, which combines selective encoding and dynamic dictionary based encoding. Depending...
Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu ...
ITC
2002
IEEE
83views Hardware» more  ITC 2002»
14 years 13 days ago
Packet-Based Input Test Data Compression Techniques
1 This paper presents a test input data compression technique, which can be used to reduce input test data volume, test time, and the number of required tester channels. The techni...
Erik H. Volkerink, Ajay Khoche, Subhasish Mitra
ATS
2003
IEEE
76views Hardware» more  ATS 2003»
14 years 25 days ago
STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data
: Most of the recently discussed test stimulus data compression techniques are based on the low care bit densities found in typical scan test vectors. Data reduction primarily is a...
Bernd Koenemann
DATE
1998
IEEE
110views Hardware» more  DATE 1998»
13 years 11 months ago
Scheduling and Module Assignment for Reducing Bist Resources
Built-in self-test BIST techniques modify functional hardware to give a data path the capability to test itself. The modi cation of data path registers into registers BIST resourc...
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breue...