12 search results - page 2 / 3 » Test Scheduling and Scan-Chain Division under Power Constrai... |
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
ASPDAC
2007
ACM
14 years 13 days ago
2007
ACM
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
ASPDAC
2012
ACM
12 years 4 months ago
2012
ACM
In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Di...