143 search results - page 10 / 29 » Test generation for designs with multiple clocks |
DATE
2002
IEEE
14 years 17 days ago
2002
IEEE
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
VLSID
2001
IEEE
14 years 8 months ago
2001
IEEE
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
FCCM
2003
IEEE
14 years 27 days ago
2003
IEEE
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
COMPUTER
2008
13 years 7 months ago
2008
ions and techniques such as activity models, storyboards, and programming by demonstration (Y. Li and J. Landay, "Activity-Based Prototyping of Ubicomp Applications for Long-L...