143 search results - page 5 / 29 » Test generation for designs with multiple clocks |
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
ITC
1992
IEEE
13 years 11 months ago
1992
IEEE
This paper presents a BIST technique that allows the synchronization of multiple scan chains clocked at different frequencies. The technique is used to improve performance testing...
VLSID
2010
IEEE
13 years 5 months ago
2010
IEEE
Directed test generation is important for the functional verification of complex system-on-chip designs. SAT based bounded model checking is promising for counterexample generatio...
IOLTS
2008
IEEE
14 years 2 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
ESSCIRC
2011
12 years 7 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...