112 search results - page 5 / 23 » Test generation in VLSI circuits for crosstalk noise |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
ASPDAC
1998
ACM
13 years 12 months ago
1998
ACM
— Simple yet useful analytical formulas for delay, slope and crosstalk noise amplitude for capacitively coupled two-, three- and infinite-line systems are derived assuming bus li...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
: Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show that in 0.13
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
We introduce a novel method of test generation for microprocessors at the RTL using spectral methods. Test vectors are generated for RTL faults, which are the stuck-at faults on i...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...