502 search results - page 3 / 101 » Test pattern generation based on arithmetic operations |
CORR
2011
Springer
13 years 3 months ago
2011
Springer
This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Inp...
VTS
2008
IEEE
14 years 2 months ago
2008
IEEE
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
ITC
1993
IEEE
14 years 20 days ago
1993
IEEE
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
DSD
2010
IEEE
13 years 7 months ago
2010
IEEE
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
IOLTS
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper proposes a new test pattern generator (TPG) which is an enhancement of GLFSR (Galois LFSR). This design is based on certain non–binary error detecting codes, formulat...