This paper investigates the impact of the changes of the characteristic polynomials and initial loadings, on behaviour of aliasing errors of parallel signature analyzer (Multi-Inp...
— Higher chip densities and the push for higher performance have continued to drive design needs. Transition delay fault testing has become the preferred method for ensuring thes...
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A...
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
This paper proposes a new test pattern generator (TPG) which is an enhancement of GLFSR (Galois LFSR). This design is based on certain non–binary error detecting codes, formulat...