72 search results - page 5 / 15 » Test register insertion with minimum hardware cost |
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
DATE
1997
IEEE
13 years 11 months ago
1997
IEEE
Many Built-In Self Test pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs o...
ISCAS
2003
IEEE
14 years 22 days ago
2003
IEEE
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
DATE
2003
IEEE
14 years 22 days ago
2003
IEEE
There have been several recent attempts to include duplication-based on-line testability in behaviourally synthesized designs. In this paper, on-line testability is considered wit...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...