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» Test set compaction algorithms for combinational circuits
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VTS
1997
IEEE
96views Hardware» more  VTS 1997»
13 years 11 months ago
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
14 years 1 months ago
Generation of compact test sets with high defect coverage
Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide hi...
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
ICCD
2003
IEEE
109views Hardware» more  ICCD 2003»
14 years 3 months ago
Independent Test Sequence Compaction through Integer Programming
We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then so...
Petros Drineas, Yiorgos Makris
ICCAD
1991
IEEE
135views Hardware» more  ICCAD 1991»
13 years 10 months ago
DIATEST: A Fast Diagnostic Test Pattern Generator for Combinational Circuits
This paper presents an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to ...
Torsten Grüning, Udo Mahlstedt, Hartmut Koopm...
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
13 years 10 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar