244 search results - page 22 / 49 » Testing Digital Circuits with Constraints |
ICCAD
2009
IEEE
13 years 7 months ago
2009
IEEE
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
ICCAD
2004
IEEE
14 years 6 months ago
2004
IEEE
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
TASE
2009
IEEE
14 years 4 months ago
2009
IEEE
The complex interactions appearing in service-oriented computing make coordination a key concern in serviceoriented systems. In this paper, we present a fault-based method to gene...
ASPDAC
2007
ACM
14 years 1 months ago
2007
ACM
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
DFT
2003
IEEE
14 years 3 months ago
2003
IEEE
In this paper, we propose a new concept of testing only functionally testable transition faults in Broadside Transition testing via a novel constrained ATPG. For each functionally...