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» Testing Digital Circuits with Constraints
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ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
14 years 6 months ago
Test-access mechanism optimization for core-based three-dimensional SOCs
— Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Su...
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yua...
DATE
2007
IEEE
138views Hardware» more  DATE 2007»
14 years 4 months ago
An ADC-BiST scheme using sequential code analysis
This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysi...
Erdem Serkan Erdogan, Sule Ozev
VLSID
2006
IEEE
92views VLSI» more  VLSID 2006»
14 years 10 months ago
A Wideband Frequency-Shift Keying Demodulator for Wireless Neural Stimulation Microsystems
: This paper presents a wideband frequency-shift keying (FSK) demodulator suitable for a digital data transmission chain of wireless neural stimulation microsystems such as cochlea...
Mian Dong, Chun Zhang, Songping Mai, Zhihua Wang, ...
ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
14 years 1 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm
JCP
2007
153views more  JCP 2007»
13 years 9 months ago
An Integrated Educational Platform Implementing Real, Remote Lab-Experiments for Electrical Engineering Courses
—This paper describes an Internet-based laboratory, named Remote Monitored and Controlled Laboratory (RMCLab) developed at University of Patras, Greece, for electrical engineerin...
Dimitris Karadimas, Kostas Efstathiou