6 search results - page 1 / 2 » Testing High-Speed SoCs Using Low-Speed ATEs |
VTS
2002
IEEE
14 years 3 months ago
2002
IEEE
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate...
ET
2002
13 years 10 months ago
2002
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
ICCD
2003
IEEE
14 years 4 months ago
2003
IEEE
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
DATE
2004
IEEE
14 years 2 months ago
2004
IEEE
This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator appl...
ISVLSI
2008
IEEE
14 years 5 months ago
2008
IEEE
Re-using the network in a NoC-based system as a test access mechanism is an attractive solution as pointed out by several authors. As a consequence, testing of NoC-based SoCs is b...