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DATE
2003
IEEE
93views Hardware» more  DATE 2003»
14 years 3 months ago
Comparison of Test Pattern Decompression Techniques
Test pattern decompression techniques are bounded with the algorithm of test pattern ordering and test data flow controlling. Some of the methods could have more sophisticated sor...
Ondrej Novák
IOLTS
2005
IEEE
206views Hardware» more  IOLTS 2005»
14 years 3 months ago
A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage
This paper proposes a new test pattern generator (TPG) which is an enhancement of GLFSR (Galois LFSR). This design is based on certain non–binary error detecting codes, formulat...
Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir
IWANN
1995
Springer
14 years 1 months ago
Test Pattern Generation for Analog Circuits Using Neural Networks and Evolutive Algorithms
This paper presents a comparative analysis of neural networks, simulated annealing, and genetic algorithms in the determination of input patterns for testing analog circuits. The ...
José Luis Bernier, Juan J. Merelo Guerv&oac...
VLSID
2003
IEEE
96views VLSI» more  VLSID 2003»
14 years 10 months ago
Design Of A Universal BIST (UBIST) Structure
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
Sukanta Das, Niloy Ganguly, Biplab K. Sikdar, Pari...
ET
2000
145views more  ET 2000»
13 years 9 months ago
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
The paper presents a novel hierarchical approach to test pattern generation for sequential circuits based on an input model of mixed-level decision diagrams. A method that handles,...
Jaan Raik, Raimund Ubar