TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to i...
Intaik Park, Ahmad A. Al-Yamani, Edward J. McClusk...
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signicant area overhead and performance degradation...
This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but explo...
Michael A. Kochte, Christian G. Zoellin, Michael E...