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VTS
1996
IEEE
75views Hardware» more  VTS 1996»
14 years 2 months ago
A new test pattern generation method for delay fault testing
S. Cremoux, Christophe Fagot, Patrick Girard, Chri...
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
14 years 3 months ago
Effective TARO Pattern Generation
TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to i...
Intaik Park, Ahmad A. Al-Yamani, Edward J. McClusk...
MCS
2011
Springer
13 years 4 months ago
A trinomial test for paired data when there are many ties
Guorui Bian, Michael McAleer, Wing-Keung Wong
ICCAD
1994
IEEE
110views Hardware» more  ICCAD 1994»
14 years 2 months ago
Test pattern generation based on arithmetic operations
Existing built-in self test (BIST) strategies require the use of specialized test pattern generation hardware which introduces signi cant area overhead and performance degradation...
Sanjay Gupta, Janusz Rajski, Jerzy Tyszer
DELTA
2008
IEEE
13 years 11 months ago
Test Set Stripping Limiting the Maximum Number of Specified Bits
This paper presents a technique that limits the maximum number of specified bits of any pattern in a given test set. The outlined method uses algorithms similar to ATPG, but explo...
Michael A. Kochte, Christian G. Zoellin, Michael E...