As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...
Inherent within complex instruction set architectures such as x86 are inefficiencies that do not exist in a simpler ISAs. Modern x86 implementations decode instructions into one o...
Brian Slechta, David Crowe, Brian Fahs, Michael Fe...
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
The increasing availability of commodity multicore processors is making parallel computing available to the masses. Traditional parallel languages are largely intended for large-s...
Matthew Fluet, Mike Rainey, John H. Reppy, Adam Sh...
We present a new differential compression algorithm that combines the hash value techniques and suffix array techniques of previous work. Differential compression refers to encodi...
Ramesh C. Agarwal, Suchitra Amalapurapu, Shaili Ja...