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DAC
2003
ACM
14 years 9 months ago
Performance-impact limited area fill synthesis
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
Yu Chen, Puneet Gupta, Andrew B. Kahng
ICCAD
2002
IEEE
73views Hardware» more  ICCAD 2002»
14 years 5 months ago
Shaping interconnect for uniform current density
As the VLSI technology scaling down, the electromigration problem becomes one of the major concerns in high-performance IC design for both power network and signal interconnects. ...
Muzhou Shao, D. F. Wong, Youxin Gao, Li-Pen Yuan, ...
GLVLSI
2009
IEEE
155views VLSI» more  GLVLSI 2009»
14 years 3 months ago
Buffer design and optimization for lut-based structured ASIC design styles
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
INFOCOM
2008
IEEE
14 years 2 months ago
Maximizing Restorable Throughput in MPLS Networks
Abstract—MPLS recovery mechanisms are increasing in popularity because they can guarantee fast restoration and high QoS assurance. Their main advantage is that their backup paths...
Reuven Cohen, Gabi Nakibly
ISCC
2005
IEEE
14 years 2 months ago
Optimal Delay-Constrained Minimum Cost Loop Algorithm for Local Computer Network
This study deals with the Delay-Constrained Minimum Cost Loop Problem (DC-MCLP) of finding several loops from a source node. The DC-MCLP consists of finding a set of minimum cost ...
Yong-Jin Lee, Mohammed Atiquzzaman