Sciweavers

287 search results - page 56 / 58
» The Case for a Single-Chip Multiprocessor
Sort
View
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
14 years 1 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
SPAA
2005
ACM
14 years 27 days ago
Value-maximizing deadline scheduling and its application to animation rendering
We describe a new class of utility-maximization scheduling problem with precedence constraints, the disconnected staged scheduling problem (DSSP). DSSP is a nonpreemptive multipro...
Eric Anderson, Dirk Beyer 0002, Kamalika Chaudhuri...
EMSOFT
2005
Springer
14 years 27 days ago
High-level real-time programming in Java
Real-time systems have reached a level of complexity beyond the scaling capability of the low-level or restricted languages traditionally used for real-time programming. While Met...
David F. Bacon, Perry Cheng, David Grove, Michael ...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 13 days ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
ASPLOS
2000
ACM
13 years 11 months ago
Hoard: A Scalable Memory Allocator for Multithreaded Applications
Parallel, multithreaded C and C++ programs such as web servers, database managers, news servers, and scientific applications are becoming increasingly prevalent. For these applic...
Emery D. Berger, Kathryn S. McKinley, Robert D. Bl...