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» The Delayed k-Server Problem
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DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 10 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...
TNN
2008
102views more  TNN 2008»
13 years 8 months ago
Robust Synchronization of an Array of Coupled Stochastic Discrete-Time Delayed Neural Networks
Abstract--This paper is concerned with the robust synchronization problem for an array of coupled stochastic discrete-time neural networks with time-varying delay. The individual n...
J. Liang, Z. Wang, Y. Liu, X. Liu
FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
14 years 3 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
ISQED
2006
IEEE
116views Hardware» more  ISQED 2006»
14 years 2 months ago
Probabilistic Delay Budgeting for Soft Realtime Applications
Unlike their hard realtime counterparts, soft realtime applications are only expected to guarantee their ”expected delay” over input data space. This paradigm shift calls for ...
Soheil Ghiasi, Po-Kuan Huang
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
14 years 2 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....