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DATE
2010
IEEE
184views Hardware» more  DATE 2010»
14 years 20 days ago
An analytical method for evaluating Network-on-Chip performance
Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and becom...
Sahar Foroutan, Yvain Thonnart, Richard Hersemeule...
AOSE
2005
Springer
14 years 1 months ago
Automating Model Transformations in Agent-Oriented Modelling
Abstract. Current Agent-Oriented Software Engineering (AOSE) methodologies adopt a model-based approach for analysis and design, but, in order to become of practical use, they shou...
Anna Perini, Angelo Susi
DAC
2009
ACM
14 years 8 months ago
Process variation characterization of chip-level multiprocessors
Within-die variation in leakage power consumption is substantial and increasing for chip-level multiprocessors (CMPs) and multiprocessor systems-on-chip. Dealing with this problem...
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, ...
DAC
2010
ACM
13 years 11 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
ISCA
2008
IEEE
205views Hardware» more  ISCA 2008»
14 years 2 months ago
VEAL: Virtualized Execution Accelerator for Loops
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...
Nathan Clark, Amir Hormati, Scott A. Mahlke