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» The Design and Optimization of SOC Test Solutions
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ICCAD
2001
IEEE
113views Hardware» more  ICCAD 2001»
14 years 3 months ago
The Design and Optimization of SOC Test Solutions
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
Erik Larsson, Zebo Peng, Gunnar Carlsson
ET
2002
105views more  ET 2002»
13 years 6 months ago
An Integrated Framework for the Design and Optimization of SOC Test Solutions
We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for...
Erik Larsson, Zebo Peng
DATE
2009
IEEE
98views Hardware» more  DATE 2009»
14 years 1 months ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimizat...
Li Jiang, Lin Huang, Qiang Xu
VTS
2003
IEEE
81views Hardware» more  VTS 2003»
14 years 2 days ago
Test Resource Partitioning and Optimization for SOC Designs
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
Erik Larsson, Hideo Fujiwara
DATE
2005
IEEE
119views Hardware» more  DATE 2005»
14 years 13 days ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen