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» The High Level Architecture for Simulations
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ISCAS
2002
IEEE
95views Hardware» more  ISCAS 2002»
14 years 1 months ago
A differential DAC architecture with variable common-mode level
A differential current-steering digital-to-analog converter (DAC) architecture allowing the common-mode level of the input signal to be varied is presented. Simulation results wit...
K. Ola Andersson, N. U. Andersson, Mark Vesterback...
DATE
2000
IEEE
86views Hardware» more  DATE 2000»
14 years 1 months ago
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level
Simulation is still one of the most important subtasks when designing a VLSI circuit. However, more and more elements on a chip increase simulation runtimes. Especially on transis...
Norbert Fröhlich, Volker Gloeckel, Josef Flei...
ISPASS
2007
IEEE
14 years 3 months ago
PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...
Matt T. Yourst
HPCA
2000
IEEE
14 years 1 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
EVOW
2001
Springer
14 years 1 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...