379 search results - page 58 / 76 » The Imagine Stream Processor |
MICRO
2002
IEEE
14 years 18 days ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...
LCPC
2001
Springer
14 years 4 days ago
2001
Springer
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
ISCA
2000
IEEE
14 years 2 days ago
2000
IEEE
Trace caches enable high bandwidth, low latency instruction supply, but have a high miss penalty and relatively large working sets. Consequently, their performance may suffer due ...
ISCA
1999
IEEE
13 years 12 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
MICRO
1999
IEEE
13 years 12 months ago
1999
IEEE
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...