41 search results - page 5 / 9 » The Latency Hiding Effectiveness of Decoupled Access Execute... |
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
ASPLOS
2004
ACM
14 years 23 days ago
2004
ACM
This paper introduces a compiler-orchestrated prefetching system as a unified framework geared toward ameliorating the gap between processing speeds and memory access latencies. ...
ISCA
2000
IEEE
13 years 11 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
ISCA
1996
IEEE
13 years 11 months ago
1996
IEEE
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory laten...
APCSAC
2004
IEEE
13 years 11 months ago
2004
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory. This paper is a first look at the value of RAMpage to ...