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ATS
2003
IEEE
110views Hardware» more  ATS 2003»
14 years 2 months ago
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of thes...
Yu-Chiun Lin, Shi-Yu Huang
DATE
2003
IEEE
112views Hardware» more  DATE 2003»
14 years 2 months ago
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula
System design methodology is poised to become the next big enabler for highly sophisticated electronic products. Design verification continues to be a major challenge and simulat...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
IRI
2003
IEEE
14 years 2 months ago
A Formal Framework for Design Component Contracts
– Building large software systems out of existing software components can save time and cost. These software components range from architectural and design components to binary c...
Jing Dong, Paulo S. C. Alencar, Donald D. Cowan
ITC
2003
IEEE
106views Hardware» more  ITC 2003»
14 years 2 months ago
Detection of Resistive Shorts in Deep Sub-micron Technologies
Current-based tests are the most effective methods available to detect resistive shorts. Delta IDDQ testing is the most sensitive variant and can handle off-state currents of 10-1...
Bram Kruseman, Stefan van den Oetelaar
VTS
2003
IEEE
115views Hardware» more  VTS 2003»
14 years 2 months ago
Fault Testing for Reversible Circuits
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
Ketan N. Patel, John P. Hayes, Igor L. Markov